FPGA implementation of efficient logarithmic multiplier

Abstract

Multipliers are inevitable components in Signal processing and Image Processing Applications. Their performance is often
limited by the speed and large area. The Logarithmic Number System (LNS) has played a vital role in the field of
addressing these issues. The proposed work involves realizing efficient VLSI architectures for Logarithmic multiplication
using Mitchell’s method, Operand decomposition which is advantageous compared to conventional multipliers in terms of
speed and area. The proposed multiplier can be utilized in digital filters of DSP applications. The efficiency of the
multiplier is still improved by using VLSI DSP techniques. The proposed work is simulated using Verilog followed by
synthesis using Xilinx ISE 14.1 and is implemented in Spartan -6 FPGA. The performance of the proposed architecture is
analyzed in terms of hardware, area and speed.