FPGA implementation of efficient logarithmic multiplier

Authors

G. Shobana,G. Prema,K. Preethi

Keywords:

Logarithmic Number System (LNS), Mitchell Method (MA), Operand Decomposition (OD), VLSI DSP Techniques

Abstract

Published

19191919-June06-3030

Issue

Vol. 46 No. 3 (2019)

Section

Articles